PKW4=|**SystemVerilog.tmLanguage fileTypes sv SV foldingStartMarker (begin)\s*(//.*)?$ foldingStopMarker ^\s*(begin)$ name System Verilog patterns match \b(automatic|cell|config|deassign|defparam|design|disable|edge|endconfig|endgenerate|endspecify|endtable|endtask|event|generate|genvar|ifnone|incdir|instance|liblist|library|localparam|macromodule|negedge|noshowcancelled|posedge|pulsestyle_onevent|pulsestyle_ondetect|real|realtime|scalared|showcancelled|specify|specparam|table|task|time|use|vectored|new)\b name keyword.other.systemverilog match \b(#|@|begin|end|fork|join|join_any|join_none|forkjoin|{|})\b name keyword.other.systemverilog match \b(initial|always|wait|force|release|assign|always_comb|always_ff|always_latch|forever|repeat|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|randomize|with|inside|dist|clocking|cover|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|modport|matches|solve|static|assert|assume|before|expect|bind|extends|sequence|var|cross|ref|first_match|srandom|time|struct|packed|final|chandle|alias|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|uwire|wait_order|triggered|randsequence|import|export|context|pure|intersect|wildcard|within|virtual|local|const|typedef|enum|protected|this|super|endmodule|endfunction|endprimitive|endclass|endpackage|endsequence|endprogram|endclocking|endproperty|endgroup|endinterface)\b name keyword.control.systemverilog match \b(std)\b:: name support.class.systemverilog match \.(atob|atohex|atoi|atooct|atoreal|bintoa|hextoa|itoa|octtoa|realtoa|len|getc|putc|toupper|tolower|compare|icompare|substr|num|exists|first|last|name|index|find|find_first|find_last|find_index|find_first_index|find_last_index|min|max|unique|unique_index|sort|rsort|shuffle|reverse|sum|product|xor|status|kill|self|await|suspend|resume|get|put|peek|try_get|try_peek|try_put|data|eq|neq|next|prev|new|size|delete|empty|pop_front|pop_back|front|back|insert|insert_range|erase|erase_range|set|swap|clear|purge|start|finish)\b name support.function.systemverilog match \b(get_randstate|set_randstate)\b name support.function.systemverilog match \b(null|void)\b name support.constant.systemverilog captures 1 name keyword.other.systemverilog 2 name entity.name.type.include.systemverilog match ^\s*(`include)\s+(["<].*[">]) name meta.include.systemverilog match `(celldefine|default_nettype|define|else|elsif|endcelldefine|endif|ifdef|ifndef|include|line|nounconnected_drive|resetall|timescale|unconnected_drive|undef|begin_\w+|end_\w+|remove_\w+|restore_\w+)\b name constant.other.preprocessor.systemverilog match `\b([a-zA-Z_][a-zA-Z0-9_]*)\b name constant.other.define.systemverilog include #comments captures 1 name storage.type.systemverilog 2 name entity.name.type.class.systemverilog match \b(function)\s+\b([a-zA-Z_][a-zA-Z0-9_]*)\b name meta.definition.systemverilog captures 1 name storage.type.systemverilog 2 name entity.name.type.class.systemverilog match ^\s*(module|function|primitive|class|package|constraint|interface|covergroup|program)\s+\b([a-zA-Z_][a-zA-Z0-9_]*)\b name meta.definition.systemverilog include #all-types match (==|===|!=|!==|<=|>=|<|>) name keyword.operator.comparison.systemverilog match (\-|\+|\*|\/|%) name keyword.operator.arithmetic.systemverilog match (!|&&|\|\||\bor\b) name keyword.operator.logical.systemverilog match (&|\||\^|~|{|}|<<|>>|\?|:) name keyword.operator.bitwise.systemverilog match \b(output|input|inout|and|nand|nor|or|xor|xnor|buf|not|bufif[01]|notif[01]|r?[npc]mos|tran|r?tranif[01]|pullup|pulldown)\b name support.type.systemverilog match (\b\d+)?'([bB]\s*[0-1_xXzZ?]+|[oO]\s*[0-7_xXzZ?]+|[dD]\s*[0-9_xXzZ?]+|[hH]\s*[0-9a-fA-F_xXzZ?]+)((e|E)(\+|-)?[0-9]+)?\b name constant.numeric.systemverilog include #strings match \$\b([a-zA-Z_][a-zA-Z0-9_]*)\b name support.function.systemverilog match \b([A-Z][A-Z0-9_]+)\b name constant.other.systemverilog repository all-types patterns include #storage-type-systemverilog include #storage-modifier-systemverilog comments patterns begin /\* captures 0 name punctuation.definition.comment.systemverilog end \*/ name comment.block.systemverilog captures 1 name punctuation.definition.comment.systemverilog match (//).*$\n? name comment.line.double-slash.systemverilog storage-type-systemverilog match \b(wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|parameter|integer|rand|randc|int|longint|shortint|logic|bit|byte|shortreal|string)\b name storage.type.systemverilog storage-modifier-systemverilog match \b(signed|unsigned|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\b name storage.modifier.systemverilog strings patterns begin " beginCaptures 0 name punctuation.definition.string.begin.systemverilog end " endCaptures 0 name punctuation.definition.string.end.systemverilog name string.quoted.double.systemverilog patterns match \\. name constant.character.escape.systemverilog begin ' beginCaptures 0 name punctuation.definition.string.begin.systemverilog end ' endCaptures 0 name punctuation.definition.string.end.systemverilog name string.quoted.single.systemverilog patterns match \\. name constant.character.escape.systemverilog scopeName source.systemverilog uuid 789be04c-8b74-352e-8f37-63d336001277 PKW4=?b""verilog.tmLanguage fileTypes v V foldingStartMarker (begin)\s*(//.*)?$ foldingStopMarker ^\s*(end)$ name verilog patterns match \b(automatic|cell|config|deassign|defparam|design|disable|edge|endconfig|endgenerate|endspecify|endtable|endtask|event|generate|genvar|ifnone|incdir|include|instance|liblist|library|localparam|macromodule|negedge|noshowcancelled|posedge|pulsestyle_onevent|pulsestyle_ondetect|real|realtime|scalared|showcancelled|specify|specparam|table|task|time|use|vectored)\b name keyword.other.verilog match (#|@) name keyword.other.verilog match \b(initial|always|wait|force|release|assign)\b name keyword.control.verilog match \b(begin|end|fork|join)\b name keyword.other.verilog match \b(forever|repeat|while|for|if|else|case|casex|casez|default|endcase)\b name keyword.control.verilog captures 1 name keyword.other.verilog 2 name entity.name.type.include.verilog match ^\s*(`include)\s+(["<].*[">]) name meta.include.verilog match `(celldefine|default_nettype|define|else|elsif|endcelldefine|endif|ifdef|ifndef|include|line|nounconnected_drive|resetall|timescale|unconnected_drive|undef)\b name constant.other.preprocessor.verilog match `\b([a-zA-Z_][a-zA-Z0-9_]*)\b name constant.other.define.verilog include #comments match \b(endmodule|endfunction|endprimitive)\b name storage.type.verilog captures 1 name storage.type.verilog 2 name entity.name.type.class.verilog match ^\s*(module|function|primitive)\s+\b([a-zA-Z_][a-zA-Z0-9_]*)\b name meta.definition.verilog include #all-types match (==|===|!=|!==|<=|>=|<|>) name keyword.operator.comparison.verilog match (\-|\+|\*|\/|%) name keyword.operator.arithmetic.verilog match (!|&&|\|\||or) name keyword.operator.logical.verilog match (&|\||\^|~|{|}|<<|>>|\?|:) name keyword.operator.bitwise.verilog match \b(output|input|inout|and|nand|nor|or|xor|xnor|buf|not|bufif[01]|notif[01]|r?[npc]mos|tran|r?tranif[01]|pullup|pulldown)\b name support.type.verilog match (\b\d+)?'([bB]\s*[0-1_xXzZ?]+|[oO]\s*[0-7_xXzZ?]+|[dD]\s*[0-9_xXzZ?]+|[hH]\s*[0-9a-fA-F_xXzZ?]+)((e|E)(\+|-)?[0-9]+)?\b name constant.numeric.verilog include #strings match \$\b([a-zA-Z_][a-zA-Z0-9_]*)\b name support.function.verilog match \b([A-Z][A-Z0-9_]+)\b name constant.other.verilog repository all-types patterns include #storage-type-verilog include #storage-modifier-verilog comments patterns begin /\* captures 0 name punctuation.definition.comment.verilog end \*/ name comment.block.verilog captures 1 name punctuation.definition.comment.verilog match (//).*$\n? name comment.line.double-slash.verilog storage-type-verilog match \b(wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|parameter|integer)\b name storage.type.verilog storage-modifier-verilog match \b(signed|unsigned|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\b name storage.modifier.verilog strings patterns begin " beginCaptures 0 name punctuation.definition.string.begin.verilog end " endCaptures 0 name punctuation.definition.string.end.verilog name string.quoted.double.verilog patterns match \\. name constant.character.escape.verilog begin ' beginCaptures 0 name punctuation.definition.string.begin.verilog end ' endCaptures 0 name punctuation.definition.string.end.verilog name string.quoted.single.verilog patterns match \\. name constant.character.escape.verilog scopeName source.verilog uuid 6856ea09-6f82-3ead-a3ae-2dd2d81453b9 PKW4= VV README.txtAdds support for editing Verilog filetypes (*.v, *.V) and SystemVerilog files (sv, SV)PKW4=|**SystemVerilog.tmLanguagePKW4=?b""/+verilog.tmLanguagePKW4= VV _MREADME.txtPKM